ChibiOS Free Embedded RTOS

Hi Bob,

thank you for your support!

The pal callback approach with the extra GPIO pin looks good to me. I will try that one asap as I added the extra circuitry.

BR
Skadi

Hi Bob, thank you for your reply. Hi, To use the timer purely as a DMA trigger there is no need to involve Slave Mode. You don't care about the timer value in such a use case. Just the trigger event. So just leave SMCR reset. Capture Input mode will produce a CC event at the edge transition(s) of th...

Hi, I have designed a new PCB including a STM32F4 connected to an external simultaneous sampling ADC. The ADC provides the data also interleaved on a parallel port. Unfortunately this ADC provides a single clock, so I have no further possebility to double check the data output clock state. I'm using...

Hi Giovanni,

I followed your suggestion, but I get the same error massage.

BR

Hi Giovanni, I had a look at the .map file, where I found the following Memory Configuration: Name Origin Length Attributes flash 0x08000000 0x00200000 ram0 0x20000000 0x00030000 ram1 0x20000000 0x0001c000 ram2 0x2001c000 0x00004000 ram3 0x20020000 0x00010000 ram4 0x10000000 0x00010000 ram5 0x400240...

Hi, I'm running ChibiOS on a STM32F429VI which has 2048 kB Flash and 256 kB RAM . What I'm trying to do, is to allocate a static array like static uint16_t Buffer[X] = {0}; I curious what's the maximum static array size can be. For an array size up to X = 64800 , compiling works fine. For a larger a...

Hi,

I'm still not able to use the pins PH0 and PH1 as GPIO pins, as stated in my previous post. Has anyone an idea how I can fix this or what I made propably wrong?

BR

Hi, @ rew: To avoid an too early data acquisition, and therefor inccorect data (pair) reading, I added the following code lines. Which proofs the state of an additional ADC clock, indicating two now samples (for the same time instance). So I ensure the correct LOW to HIGH transition at this pin, tha...

Hi Giovanni, I analyzed my fetched in data further. I figured out what went wrong. As I already mentioned, the data of the two ADC channels are interleaved clocked out on the rising edge of the clock line. The correct data stream for 10 consecutive data would look like as following: CH1(t1) ...

Hi, I designed a PCB including a STM32F429, which is connected to an two channels (16Bit) simultaneous sampling ADC. The ADC has two inputs, which are sampled at the same time instance. The results are interleaved clocked out on the rising edge of an data clock source provided by the ADC. This clock...